Complex SoC products, for example, products for analog voltage detection and for joystick control, often contain embedded comparators. The performance of these comparators needs to be tested to detect manufacturing faults and to ensure that the products function according to their specifications. Conventional methods of testing involve either reliance on functional testing wherein the whole circuit of which the comparator forms a part is tested or the implementation of a special test mode wherein the input and output of the comparator are made accessible at chip pins in order that the off-chip test circuit can be used to test the functioning of the comparator.
However, neither of these methods is entirely satisfactory. Functional testing wherein the whole of a comparator-containing circuit is tested may not be able to test the comparator itself sufficiently. Many different tests may have to be devised in an attempt to test the operation of the comparator and this is time consuming and, therefore, costly.
In contrast, off-chip testing of a comparator via a test mode involves either the use of additional chip pins, where the total number for any given chip circuitry may be limited, or analog multiplexing control, which is required to share access to analog I/O pins. Also, in order to test a high performance comparator which has a small input voltage resolution and high speed, high performance and high cost test instruments are required. Delays associated with off-chip connection loading limit the frequency of input test signals and high speed buffers are therefore required to drive the outputs off-chip. These buffers limit the testing accuracy and increase test costs. In addition, the loading caused by such analog test-paths may degrade the functional performance of the embedded comparator under test.